Designs and Implementations of Low-Leakage Digital Standard Cells Based on Gate-Length Biasing
نویسندگان
چکیده
منابع مشابه
Designs and Implementations of Low-Leakage Digital Standard Cells Based on Gate- Length Biasing
In this study, a minimum set of low-power digital standard cells for low-leakage applications are developed and introduced into SMIC (Semiconductor Manufacturing International Corporation) 130 nm CMOS libraries, which include basic logic gates such as inverter, NAND, NOR, XOR, XNOR and flip-flop. The inverter, NAND, NOR and flip-flop standard cells based on the gate-length biasing technique are...
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With the technology process scaling, leakage power dissipation is becoming a growing number of percentage in total power dissipation. This study presents a new method in the gate-length biasing technique to achieve a cost-effective gate-length with a most benefit between leakage reduction and delay increasing. With the optimized gate-length, typical combinational and sequential circuits are rea...
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15 صفحه اولGate Leakage
1) Introduction Recent systems are built of MOSFET transistors. Here, MO stands for metal oxide and FE for field effect. This means, that – in contrast to bipolar transistors – the gate is isolated by a metal oxide (today SiO2) and the channel is just controlled by the field through this oxide. Thus theoretically, the principal of MOSFET devices is that there is no current flowing through the g...
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ژورنال
عنوان ژورنال: Research Journal of Applied Sciences, Engineering and Technology
سال: 2013
ISSN: 2040-7459,2040-7467
DOI: 10.19026/rjaset.5.4606